Sample Verilog Programs from Wikipedia
http://en.wikipedia.org/wiki/Verilog

NOTE: Only examples 1&2 are complete programs.


--------------------------------------- Example 1: Two flip-flops
module toplevel(clock,reset);
    input clock;
    input reset;

    reg flop1;
    reg flop2;

    always @ (posedge reset or posedge clock) 
    if (reset)
        begin
        flop1 <= 0;
        flop2 <= 1;
        end
    else
        begin
        flop1 <= flop2;
        flop2 <= flop1;
        end
endmodule

--------------------------------------- Example 2: Counter
module Div20x (rst, clk, cet, cep, count,tc);
//TITLE   'Divide-by-20 Counter with enables'

//enable CEP is a clock enable only
//enable CET is a clock enable and enables the TC output

    parameter size = 5;
    parameter length = 20;

    input rst;  // These inputs/outputs represent connections to
    input clk;  // the module.  
    input cet;
    input cep;

    output [size-1:0] count; 
    output tc;

    reg [size-1:0] count;  // Signals assigned within an always (or initial) block
                           // must be of type reg
    wire tc;               // Other signals are of type wire
    
    // The always statement below is a parallel execution statement that
    // executes any time the signals rst or clk transition from low to high
    always @ (posedge rst or posedge clk) 
                 
       if (rst)             // This simulates a reset of the counter                   
           count <= 5'b0;
       else 
       if (cet && cep) // This simulates the enables both being true
         begin
           if (count == length-1)
              count <= 5'b0;
           else
              count <= count + 5'b1;  // 5'b1 is 5 bits wide and 
         end                          // equal to the value 1.


    // the value of tc is continuously assigned the value of the expression
    assign tc = (cet && (count == length-1));

endmodule

--------------------------------------- Example 3: Delays
... // code elided
reg a, b, c, d;
wire e;
... // code elided
always @(b or e)
  begin
     a = b & e;
     b = a | b;
     #5 c = b;  // c assinged to b after delay of 5 time units
     d = #6 c ^ e;  // after 6 more time units, d is assigned
  end

--------------------------------------- Example 4: Constants
12'h123 - Hexidecimal 123 (using 12 bits)
20'd44 - Decimal 44 (using 20 bits)
4'b1010 - Binary 4 (using 4 bits)
6'o77 - Octal 77 (using 6 bits)

--------------------------------------- Example 5: Basic hardware representation templates
// Mux examples
// The first example uses continuous assignment

wire wire_out ;

assign  wire_out = sel ? a : b;

// the second example uses a procedure to accomplish
// the same thing. 

reg reg_out;
always @(a or b or sel)
  reg_out = sel ? a: b;

// Finally - you can use if/else in a procedural structure.
reg if_out;
always @(a or b or sel)
  if (sel)
       if_out = a;
  else
       if_out = b;

--------------------------------------- Example 6: Latch
reg latch_out;
always @(gate or din)
  if(gate)
      latch_out = din;  // Pass through state
                        // Note that the else isn't required
                        // here. The variable will follow
                        // the value of din while the signal
                        // gate is high. when gate goes low,
                        // latch_out will remain constant.

--------------------------------------- Example 7: Basic D flop
reg q;
always @(posedge clk)
  q <= d;

--------------------------------------- Example 8: Flop with asynchronous reset
reg q;
always @(posedge clk or posedge reset)
  if(reset == 1)
    q <= 0;
  else
    q <= d;

--------------------------------------- Example 9: Flop with asynchronous reset & set
reg q;
always @(posedge clk or posedge reset or posedge set)
  if(reset == 1)
    q <= 0;
  else
  if(set == 1)
    q <= 1;
  else
    q <= d;

--------------------------------------- Example 10: Flop with a mux feeding its input
// Basic structure with feedback path illustrated
always @(posedge clk)
  if(gate)
    q <= d;
  else
    q <= q;

// The more common structure ASSUMES the feedback is present
// This is a safe assumption since this is how the
// hardware compiler will interpret it.  This structure
// looks much like a Latch. The differences are the
// @(posedge clk) and the non-blocking <=
// 
always @(posedge clk)
  if(gate)
    q <= din;  // the mux is "implied"

--------------------------------------- Most frequently used system tasks
$display - Print a line followed by an automatic newline. 
$write - Print a line without the newline. 
$readmemh - Read hex file content into a memory array. 
$readmemb - Read binary file content into a memory array. 
$monitor - Print out all the listed variables when any change value. 
$time - Value of current simulation time. 
$dumpfile - Declare the VCD ( Value Change Dump ) format output file name. 
$dumpvars - Turn on and dump the variables. 
$random - Return a random value.