Selected portions of the Verilog BNF
(from http://www.verilog.com/VerilogBNF.html)
verishort vitalog


Definition of Items in Formal Syntax Specifications:
+-----------------------+------------------------------------------------------------+
|      Item             |               Meaning                                      |
+-----------------------+------------------------------------------------------------+
| White space           | may be used to separate lexical tokens                     |
+-----------------------+------------------------------------------------------------+
| Angle brackets        | surround each description item and are not literal sym-    |
|                       | bols. That is, they do not appear in the source descrip-   |
|                       | tion. Any text outside angle brackets is literal.          |
+-----------------------+------------------------------------------------------------+
| <name> in lower case  | is a syntax construct item                                 |
+-----------------------+------------------------------------------------------------+
| <NAME> in upper case  | is a lexical token item. Its definition is a terminal node |
|                       | in the description hierarchy -- that is, its definition    |
|                       | does not contain any syntax construct items                |
+-----------------------+------------------------------------------------------------+
| <name>?               | is an optional item                                        |
+-----------------------+------------------------------------------------------------+
| <name>*               | is zero, one, or more items                                |
+-----------------------+------------------------------------------------------------+
| <name>+               | is one or more items                                       |
+-----------------------+------------------------------------------------------------+
| <name><,<name>>*      | is a comma-separated list of items with at least one       |
|                       | item in the list                                           |
+-----------------------+------------------------------------------------------------+
| <name>::=             | gives a syntax definition to an item                       |
+-----------------------+------------------------------------------------------------+
| ||=                   | introduces an alternative syntax definition                |
+-----------------------+------------------------------------------------------------+




1. Source Text

<source_text>
	::= <description>*

<description>
	::= <module>

<module> // Modules are similar to functions in other programming languages;
         // they contain inputs, outputs, bidirectional ports, wires,
         // and registers--relationships between these elements are expressed
         // by concurrent and sequential statements.
	::= module <name_of_module> <list_of_ports>? ;
		<module_item>*
		endmodule

<name_of_module>
	::= <IDENTIFIER>

<list_of_ports>
	::= ( <port> <,<port>>* )

<port>  // An implicit internal connection is created connecting the port to a
        // net or register of the same name as the port.
	::= <port_expression>?

<port_expression>
	::= <port_reference>

<port_reference>
	::= <name_of_variable>

<name_of_variable>
	::= <IDENTIFIER>

<module_item>
        // Parameters are constants, usually used to specify delays and
        // width of variables.
        ::= <parameter_declaration>
	||= <input_declaration>
	||= <output_declaration>
	||= <inout_declaration>
        // Only wire type nets appear in this restricted grammar. 
	||= <net_declaration>
        // Registers are data storage elements (nets and registers are the
        // two main data groups).
	||= <reg_declaration>
        // Continuous assignment statements occur outside of procedures
        // (initial, always, function and task are the 4 types of procedures).
	||= <continuous_assign>
        // An always block will run, simultaneous with other always blocks,
        // whenever one or more of its conditions is fulfilled.
	||= <always_statement>
	||= <gate_declaration>


2. Declarations

// ************************ Parameter (constants) related
<parameter_declaration>
	::= parameter <list_of_param_assignments> ;

<list_of_param_assignments>
	::=<param_assignment><,<param_assignment>*

<param_assignment>
	::=<identifier> = <constant_expression>
// ************************ end Parameter (constants) related

// ************************ Input/Output ports declaration related
<input_declaration>
	::= input <range>? <list_of_variables> ;

<output_declaration>
	::= output <range>? <list_of_variables> ;

<inout_declaration>
	::= inout <range>? <list_of_variables> ;
// ************************ end Input/Output ports declaration related

// ************************ Net declaration related
<net_declaration>
	::= <NETTYPE> <expandrange>? <delay>? <list_of_variables> ;

<NETTYPE> is one of the following keywords:
	wire

<expandrange>
	::= <range>
// ************************ end Net declaration related

// ************************ Gate declaration related
<gate_declaration>  // Drive strength option eliminated.
	::= <GATETYPE> <delay>?  <gate_instance> <,<gate_instance>>* ;

<GATETYPE> is one of the following keywords:
	and  nand  or  nor xor  xnor

<gate_instance>
	::= <name_of_gate_instance>? ( <terminal> <,<terminal>>* )

<name_of_gate_instance>
	::= <IDENTIFIER><range>?

<terminal>
	::= <expression>
	||= <IDENTIFIER>
// ************************ end Gate declaration related

<reg_declaration>
	::= reg <range>? <list_of_register_variables> ;

<continuous_assign>
        // Removed <drive_strength>? from after assign keyword.
	::= assign <delay>? <list_of_assignments> ;

<list_of_variables>
	::= <name_of_variable> <,<name_of_variable>>*

<name_of_variable>
	::= <IDENTIFIER>

<list_of_register_variables>
	::= <register_variable> <,<register_variable>>*

<register_variable>
	::= <name_of_register>

<name_of_register>
	::= <IDENTIFIER>

<range>
	::= [ <constant_expression> : <constant_expression> ]

<list_of_assignments>
	::= <assignment> <,<assignment>>*


3. Primitive Instances

<delay>
	::= # <number>
	||= # <identifier>
	

4. Module Instantiations


5. Behavioral Statements

<always_statement>
	::= always <statement>

<statement_or_null>
	::= <statement>
	||= ;

<statement>
        // Blocking assignments contain the = token and block the
        // continuation of the procedure until they are completed.
	::= <blocking_assignment> ;
        // Non-blocking assignments contain the <= token.  The RHS of the
        // assignment is executed immidiately, but the LHS is evaluated only
        // after all other operations in the current time step are executed.
	||= <non_blocking_assignment> ;
	||= if ( <expression> ) <statement_or_null>
	||= if ( <expression> ) <statement_or_null> else <statement_or_null>
	||= <delay_or_event_control> <statement_or_null>
        // Block of statements to exceute sequentially, enclosed by begin/end.
	||= <seq_block>
        // System tasks serve to generate input and output in a simulation.
	||= <system_task_enable>
        // This is the proceduaral type of assignment, used for assigning
        // values to register variables (continuous assingments assign to
        // wire and tri data types).
	||= assign <assignment> ;

<assignment>
	::= <lvalue> = <expression>

<blocking_assignment>
	::= <lvalue> = <expression>
        // Use of #, @ (posedge clk) are delay and event control.
	||= <lvalue> = <delay_or_event_control> <expression> ;

<non_blocking_assignment>
	::= <lvalue> <= <expression>
	||= <lvalue> = <delay_or_event_control> <expression> ;

<delay_or_event_control>
	::= <delay_control>
	||= <event_control>

<seq_block>
	::= begin <statement>* end

<system_task_enable>
	::= <name_of_system_task> ;
	||= <name_of_system_task> ( <expression> <,<expression>>* ) ;

<name_of_system_task>
	::= $<system_identifier> (Note: the $ may not be followed by a space.)

<SYSTEM_IDENTIFIER>
	An <IDENTIFIER> assigned to an existing system task or function


6. Specify Section


7. Expressions

<lvalue>
	::= <identifier>
	||= <identifier> [ <expression> ]
	||= <identifier> [ <constant_expression> : <constant_expression> ]

<constant_expression>
	::=<expression>

<mintypmax_expression>
	::= <expression>
	||= <expression> : <expression> : <expression>

<expression>
	::= <primary>
	||= <UNARY_OPERATOR> <primary>
	||= <expression> <BINARY_OPERATOR> <expression>
	||= <expression> <QUESTION_MARK> <expression> : <expression>
	||= <STRING>


<UNARY_OPERATOR> is one of the following tokens:
	+  -  !  ~  &  ~&  |  ^|  ^  ~^

<BINARY_OPERATOR> is one of the following tokens:
	+  -  *  /  %  ==  !=  ===  !==  &&  ||  <  <=  >  >=  &  |  ^  ^~  >>  <<

<QUESTION_MARK> is ? (a literal question mark).

<STRING> is text enclosed in "" and contained on one line.

<primary>
	::= <number>
	||= <identifier>
	||= <identifier> [ <expression> ]
	||= <identifier> [ <constant_expression> : <constant_expression> ]
	||= ( <mintypmax_expression> )

<number>
	::= <DECIMAL_NUMBER>
	||= <UNSIGNED_NUMBER>? <BASE> <UNSIGNED_NUMBER>
	||= <DECIMAL_NUMBER>.<UNSIGNED_NUMBER>
	||= <DECIMAL_NUMBER><.<UNSIGNED_NUMBER>>?
		E<DECIMAL_NUMBER>
	||= <DECIMAL_NUMBER><.<UNSIGNED_NUMBER>>?
		e<DECIMAL_NUMBER>
	(Note: embedded spaces are illegal in Verilog numbers, but embedded underscore
	characters can be used for spacing in any type of number.)

<DECIMAL_NUMBER>
	::= A number containing a set of any of the following characters, optionally preceded by + or -
	 	0123456789_

<UNSIGNED_NUMBER>
	::= A number containing a set of any of the following characters:
	        0123456789_

<NUMBER>
	Numbers can be specified in decimal, hexadecimal, octal or binary, and may
	optionally start with a + or -.  The <BASE> token controls what number digits
	are legal.  <BASE> must be one of d, h, o, or b, for the bases decimal,
	hexadecimal, octal, and binary respectively. A number can contain any set of
	the following characters that is consistent with <BASE>:
	0123456789abcdefABCDEFxXzZ?

<BASE> is one of the following tokens:
	'b   'B   'o   'O   'd   'D   'h   'H


8. General 

<comment>
	::= <short_comment>
	||= <long_comment>

<short_comment>
	::= // <comment_text> <END-OF-LINE>

<long_comment>
	::= /* <comment_text> */

<comment_text>
	::= The comment text is zero or more ASCII characters

<identifier>
	::= <IDENTIFIER><.<IDENTIFIER>>*
	(Note: the period may not be preceded or followed by a space.)

<IDENTIFIER>
	An identifier is any sequence of letters, digits, dollar signs ($), and
	underscore (_) symbol, except that the first must be a letter or the
	underscore; the first character may not be a digit or $. Upper and lower case
	letters are considered to be different. Identifiers may be up to 1024
	characters long. Some Verilog-based tools do not recognize  identifier
	characters beyond the 1024th as a significant part of the identifier. Escaped
	identifiers start with the backslash character (\) and may include any
	printable ASCII character. An escaped identifier ends with white space. The
	leading backslash character is not considered to be part of the identifier.

<delay_control>
	::= # <number>
	||= # <identifier>
	||= # ( <mintypmax_expression> )

<event_control>
	::= @ <identifier>
	||= @ ( <event_expression> )

<event_expression>
	::= <expression>
	||= posedge <scalar_event_expression>
	||= negedge <scalar_event_expression>
	||= <event_expression> or <event_expression>

<scalar_event_expression>
	Scalar event expression is an expression that resolves to a one bit value.