Note: This is no longer a valid BNF because ALL items that fit into the restricted grammar were removed, whether or not the items remaining might be subsets of those removed. 1. Source Text ::= // User Defined Primitives - Verilog has some built-in // primitives for gates and switches, but not very many // The term "macromodule" can be used in the same manner as the // reserved word "module". However, macromodules do not support all // Verilog constructs that modules do. The advantage of macromodules // is that, while the programmer still sees the module hierarchy in // the code, the simulation data structure removes memory consumed // by the heirarchy if it is not truly required in the implementation. ::= macromodule ? ; * endmodule // An explicit internal connection is created connecting the port to // a signal with a different name, or a part select, bit select, or // concatenation of internal signals. ::= . ( ? ) ::= { <,>* } ::= [ ] ||= [ : ] ::= // Nets are connections between structures such as gates, and, if // not connected to such drivers will simply register a value of z // (high impedance); nets (except for trireg nets) do not store values. ::= // The integer and time register data types serve to make the code // more self-documenting. ||= ||= // Again, the real data type exists to make the code more self- // documenting. ||= // A flag (no value or storage capabilities) used to synchronize // concurrent processes. ||= ||= // Module instantiation a means of nesting modules // inside other modules. ||= // Parameter override allows for parameters to be modified at // compilation time; that is, it permitts specifying different values // for the parameters of each instance of a module. ||= // Specify blocks set up timing checks and define pin-to-pin timing // delays and specparam constants (parameters within specify blocks). ||= // Initial blocks execute only once (at time 0), and can thus be // used to assign variables' starting values. ||= // Tasks and functions group sequential statements into blocks, and // are invoked from within the module. A function differs from a task // in that a function is more restricted--it cannot: include timing // delays, drive more than one output, or call a task. ||= ||= // ************************ UDP related ::= primitive ( <,>* ) ; + ? endprimitive ::= ::= ||= ||= ::= initial = ; ::= 1'b0 ||= 1'b1 ||= 1'bx ||= 1'bX ||= 1'B0 ||= 1'B1 ||= 1'Bx ||= 1'BX ||= 1 ||= 0 ::= ::= table endtable ::= + ||= + ::= : ; ::= : : ; ::= ||= ::= + ::= * * ::= ( ) ||= ::= ::= ||= - (This is a literal hyphen, see Chapter 5 for details). is one of the following characters: 0 1 x X is one of the following characters: 0 1 x X ? b B is one of the following characters: r R f F p P n N * // ************************ end UDP related // ************************ Task and Function related ::= task ; * endtask ::= ::= function ? ; + endfunction ::= ||= integer ||= real ::= ::= ||= ||= ||= ||= ||= ||= ||= // ************************ end Task and Function related 2. Declarations // ************************ Net declaration related ::= trireg ? ? ? ; ||= ? ? ? ; is one of the following keywords: tri tri1 supply0 wand triand tri0 supply1 wor trior trireg // Vectored and scalared keywords restrict allowed vector operations. // For example, bit and part selects are not permitted with vectored. ::= scalared ::= vectored // ************************ end Net declaration related ::= time ; ::= integer ; ::= real ; ::= event <,>* ; ::= assign ? ? ; ||= ? ? ? ; ::= defparam ; ::= ::= [ : ] ::= ::= ( small ) ||= ( medium ) ||= ( large ) // ************************ Drive strength related // For a wire, the value resolves to that of the strongest driver, or to x // (signals unknown logic value) if equally strong drivers give different // values. ::= ( , ) ||= ( , ) is one of the following keywords: supply0 strong0 pull0 weak0 highz0 is one of the following keywords: supply1 strong1 pull1 weak1 highz1 // ************************ end Drive strength related ::= [ : ] ::= <,>* 3. Primitive Instances // Option without drive strength is supported in restricted grammar. ::= ? ? <,>* ; // Format used when calculations have to be made to determine the delay // (is not a single constant or variable). ::= # ( <,>? <,>?) // ************************ UDP related ::= ? ? <,>* ; ::= ::= ? ( <,>* ) ::= ? ::= ||= // ************************ UDP related 4. Module Instantiations // Section 4 covers nesting of modules in other modules. ::= ? <,>* ; ::= ::= # ( <,>* ) ::= ( ? ) ::= ? ::= <,>* ||= <,>* ::= ||= ::= nothing - this form covers the case of an empty item in a list - for example: (a, b, , d) ::= .< IDENTIFIER> ( ) 5. Behavioral Statements ::= initial ||= case ( ) + endcase // casez allows the logic value z (high impedance) to signal // that it is not necessary to compare part of the expression. // Example: 4'b1zzx : out = a; // Don't care about lower 3:1 bits ||= casez ( ) + endcase // casex treats both x and Z values as unimportant in comparison. // Example: 4'b1zzx : out = a; // Don't care about lower 3:0 bits ||= casex ( ) + endcase // The forever loop, usually found in initial statements // executes continually. Example: forever #25 clk = ~clk; ||= forever // The repeat loop executes times. ||= repeat ( ) ||= while ( ) ||= for ( ; ; ) // The wait statement halts the sequential execution until // is true. ||= wait ( ) ||= -> ; // All statements in a parallel block, enclosed by fork/join, // execute simulatneously. ||= // Task enable calls a task. ||= // Diasabling prevents the task or block from being executed. ||= disable ; ||= disable ; // Deassign serves as an "undo" button for procedural assign. ||= deassign ; // Force/release works as assign/deassign, but can be used on nets as // well as on registers and is thus useful for dealing with reset // connectivity issues. ||= force ; ||= release ; ::= <,>* : ||= default : ||= default ::= begin : * * end ::= fork * join ||= fork : * * join ::= ::= ||= ||= ||= ::= ||= ( <,>* ) ; 6. Specify Section ::= specify * endspecify ::= ||= ||= ||= ||= ||= ::= specparam ; ::=<=> ::= = ; ::= ( => ) ||= ( *> ) ::= <,>* ::= <,>* ::= ||= [ ] ||= [ : ] ::= ||= [ ] ||= [ : ] ::= the of a module input or inout terminal ::= the of a module output or inout terminal. ::= ||= ( , ) ||= ( , , ) ||= ( , , , , , ) ||= ( , , , , , , , , , , , ) ::= ::= $setup( , , <,>? ) ; ||= $hold( , , <,>? ) ; ||= $period( , <,>? ) ; ||= $width( , <,,>? ) ; ||= $skew( , , <,>? ) ; ||= $recovery( , , <,>? ) ; ||= $setuphold( , , , <,>? ) ; ::= ? <&&& >? ::= ||= ::= <&&& >? ::= posedge ||= negedge ||= ::= edge [ <,>*] ::= 01 ||= 10 ||= 0x ||= x1 ||= 1x ||= x0 ::= ||= ( ) ::= ||= ~