Verilog Preprocessor (VPP)

Verilog Preprocessor (VPP) is a tool for disciplined preprocessing of Verilog hardware descriptions. Given a description, VPP does pre-expansion (pre-elaboration) static checking, guaranteeing that expansion will produce a well-typed term. It also checks for wire widths inconsistency and array bounds violations. In case the description is well-typed the tool proceeds to the main preprocessing step which is hygienic expansion. During that phase an equivalent description that is free from parameters and iterative constructs is produced and is therefore trivially synthesizable.

Distribution

• Download distribution. This is a prototype version has been tested on Linux and Mac OS X 10.4.

Documentation

• A user guide including installation instructions is now available.
• Download PEPM'08 paper.